The present invention relates to a semiconductor device used for a switching device, and in particular, to an MIS semiconductor device drivable at a low supply voltage and having a dynamic threshold voltage and a method for producing the same.
In a CMOS circuit, a power consumption is in proportion to the square of a supply voltage, and therefore reduction in the supply voltage is effective for realizing a CMOS LSI consuming less power. However, a redaction in the supply voltage reduces the driving force of transistors and thus increases a delay time period of the circuit. The problem becomes more serious as the supply voltage is reduced. Especially, it is known that the delay time period significantly increases when the supply voltage is three times the threshold voltage or less. One conceivable solution to this problem is to reduce the threshold voltage. A reduction in the threshold voltage, however, increases a leakage current when the gate is off, and therefore causes another problem that the lower limit of the threshold voltage is restricted based on the amount of tolerable leakage current when the gate is off.
In order to alleviate this problem, a dynamic threshold voltage transistor has conventionally been proposed in, for example, F. Assaderaghi et al., xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d, IEDM94, Ext. Abst. page 809, as a transistor operable at a low supply voltage. The dynamic threshold voltage transistor realizes a high driving power at a low voltage by reducing the effective threshold voltage when the transistor is ON. FIG. 34 shows a structure of a conventional dynamic threshold voltage transistor. FIG. 34 shows a dynamic threshold voltage transistor using an SOI substrate which is disclosed in U.S. Pat. No. 5,559,368 and Japanese Laid-Open Publication No. 6-85262. FIG. 34 shows an NMOS structure, but a PMOS can also be realized by inverting the polarities.
FIG. 34A is a cross-sectional view of the conventional dynamic threshold voltage transistor using an SOI substrate. FIG. 34B is a top view of the dynamic threshold voltage transistor, and FIG. 34C is a cross-sectional view thereof across a contact region of a gate electrode and a body. Reference numeral 1000 represents a silicon substrate, reference numeral 1001 represents a buried oxide layer, reference numeral 1002 represents a source region, reference numeral 1003 represents a p-type silicon layer, reference numeral 1004 represents a drain region, reference numeral 1005 represents a gate insulating layer, reference numeral 1006 represents a gate electrode, reference numeral 1007 represents a p-type diffusion layer, and reference numeral 1008 represents a metal line.
The SOI substrate is used, and the gate electrode 1006 and the p-type silicon layer 1003 are locally shortcircuited via the p-type diffusion layer 1007 and the oversized metal line 1008. When a gate bias is applied to such a structure in which the gate electrode 1006 and the p-type silicon layer 1003 are shortcircuited, a forward bias is applied to an active region, the forward bias having an equal magnitude to that of the gate bias.
It should be noted that in this structure, the voltage to be applied to the gate electrode in order to restrict the standby current is restricted to 0.6 V or less. At or in the vicinity of 0.6 V, a lateral direction bipolar transistor is turned ON. Due to the restriction in the voltage, when the gate is OFF, the substrate is usually in the same bias state as that of the transistor, and when the gate is ON, the substrate is forwardly biased as the gate bias increases. In this manner, the threshold voltage is reduced. Therefore, the dynamic threshold voltage transistor has an equivalent leakage current to that of a general SOI transistor in the same channel state when the substrate bias (gate bias) is OFF. When the transistor is ON, a significant increase in the driving force is provided as the threshold voltage is reduced.
However, the above-described structure uses an SOI substrate. Accordingly, the body (p-type silicon layer as the channel region) has a very small thickness (50 nm to 200 nm) and thus obtains a very high resistance. Therefore, even when the gate electrode and body are shortcircuited by a contact region, it becomes more difficult to transfer the potential of the gate electrode to the body and the CR time constant becomes larger as the body is more distanced from the contact region. Thus, in terms of a transient operation, the effect of the dynamic threshold metal-oxide-silicon FET (DTMOSFET; hereinafter, referred to as the xe2x80x9cDTMOSxe2x80x9d) is restricted and the DTMOS device cannot operate at a high speed.
The source and drain regions have a great thickness and thus obtains a high resistance. It is effective to salicide the source and drain regions (self-aligned saliciding) using a refractory metal material in order to avoid the high resistance of the source and drain regions. However, it is difficult to salicide the source and drain regions which are formed of a very thin silicon layer on the oxide layer. In order to solve the problems of the DTMOS device using the SOI substrate, the present inventors proposed a dynamic threshold voltage transistor using a bulk silicon substrate (Japanese Laid-Open publication No. 10-22462). As shown in FIG. 35, the dynamic threshold voltage transistor using a bulk silicon substrate includes a MOSFET provided on a bulk silicon substrate 0301. The MOSFET includes a deep well 0302 provided on the bulk silicon substrate 0301, a shallow well 0303 having an opposite conductivity type to that of the deep well 0302 provided in the deep well 0302, and source and drain regions 0307 of a conductivity type opposite to that of the shallow well 0303 (namely, the same conductivity type as that of the deep well 0302) which are provided in the shallow well 0303. A gate electrode 0306 of the MOSFET has a feature of being electrically connected to the shallow well 0303. At least the shallow well 0303 is electrically isolated from a shallow well 03031 included in an adjacent transistor by a groove-type device isolation region 0304. Reference numeral 0305 represents a gate oxide layer, reference numeral 0308 represents an interlevel isolating layer, and reference numeral 0309 represents a contact hole.
The structure shown in FIG. 35 solves the problem of the increase in the resistance of the body of a DTMOS using an SOI substrate. However, when a bulk substrate is used, unlike the case of the SOI substrate, the planar size of the junction of the source and drain regions and the shallow well region increases, which accompanies an increase in the parasitic capacitance. The power consumption P is expressed by P=Cxc3x97V2xc3x97f where V is the supply voltage, C is the capacitance of the circuit including the parasitic capacitance, and f is the operating frequency. In other words, it is important to reduce the supply voltage, and also to reduce the capacitance, in order to lower the power consumption. As compared to the usual MOSFET having a constant potential in the well region, the DTMOS having the structure shown in FIG. 35 which shortcircuits the gate electrode and the body region or the well region is disadvantageous when the planar size of the junction of the source and drain regions and the well region is the same.
With reference to FIGS. 36 and 37, the parasitic capacitance will be described in detail. FIG. 36 shows the state of a usual CMOS inverter having a fan-out of 1. FIG. 37 shows the state of a CMOS inverter of a dynamic threshold voltage transistor having a fan-out of 1, in which the gate electrode and the well region are shortcircuited. In FIGS. 36 and 37, parasitic capacitances are indicated with xe2x80x9cxe2x88x92xe2x80x9d and xe2x80x9c+xe2x80x9d. As is easily appreciated from the comparison between FIGS. 36 and 37, the dynamic threshold voltage transistor shown in FIG. 37 has a capacitance at the junction which is three times as high as that of the junction of the usual transistor shown in FIG. 36 when the planar size of the junction is the same. In actuality, however, the capacitance is not simply three times since the area of the depletion layer is different between the forward bias portion and the reverse bias portion. FIG. 38 compares specific capacitances of the two types of transistors both having circuit of a fan-out of 2.
The transistors used for the comparison shown in FIGS. 38A and 38B have a gate length of 0.24 xcexcm. The distance between the gate electrode to the device isolation region (the width of the source and drain regions) is 0.72 xcexcm. In FIGS. 38A and 38B, CW represents a line capacitance, CG represents a gate capacitance, CDR represents a capacitance at the junction of the well region and the drain region in a reverse bias state, CDF represents a capacitance at the junction of the well region and the drain region in a forward bias state, CS represents a capacitance at the junction of the well region and the source region, CSW/DW represents a capacitance between the shallow well region and the deep well region, and Cdep represents a capacitance between the inverted channel region and the shallow well. Since the usual MOS transistor and the bulk-DTMOS (B-DTMOS) device are substantially the same in the gate capacitance CG and the line capacitance CW, the usual transistor and the dynamic threshold voltage transistor are compared with the other capacitances. When CW is 10 fF (see FIG. 38A), the usual transistor has only the CDR, which is 4.7 whereas the dynamic threshold voltage transistor has a total capacitance of CDR+CDF+CS+CSW/DW+Ddep, which is 28.5. Namely, the junction parasitic capacitance of the bulk DTMOS device is about 6 times as large as that of the usual transistor when compared using a circuit having a fan-out of 2. This problem of the parasitic capacitance is caused even when an SOI substrate is used. When CW is as large as 100 fF as in FIG. 38B, the junction parasitic capacitance of CDR+CDF+Cg+CSW/DW+Ddep is 9.2, which is smaller than the above-mentioned value of 28.5. As the size of the device is reduced, the ratio of the line capacitance is increased since the line capacitance cannot be reduced in proportion to the size of the device. The ratio of the junction parasitic capacitance is decreased but not to a negligible level. (For example, even in the case of FIG. 38B, the capacitance is increased by about 8% as can be appreciated from the ratio of 100:107.8). Therefore, it is important to reduce the junction parasitic capacitance.
A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; a gate electrode side wall insulating layer provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to portions of the gate electrode side wall insulating layer so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other, and the second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.
The structure according to the present invention has a function of reducing the parasitic resistance of the source and drain regions. The structure according to the present invention significantly facilitates siliciding of the source and drain regions which is conventionally very difficult. According to the structure of the present invention, impurity ions to act as donors or acceptors for forming the source and drain regions can be implanted only into a second conductivity type semiconductor region (more precisely, the region becomes of the second conductivity type as a result of the implantation) accumulated above the channel region and can be diffused from the accumulated region into the solid layer, i.e., the semiconductor substrate. Thus, the junction can be formed. Therefore, the short channel effect resulting from size reduction of the device is effectively suppressed. The surface area of the source drain regions can be larger than the planar size thereof. Therefore, the contact region of the source and drain regions and upper lines can be enlarged so as to reduce the contact resistance with respect to the planar size of the source and drain regions.
In terms of saliciding (self-aligned salicide), the surface area which is to be salicided is large with respect to the planar size. Accordingly, the resistance is reduced, and the undesirable influence of the thin lines occurring at the time of siliciding reaction (i.e., the siliciding reaction of the thin lines is inhibited) is alleviated. The structure according to the present invention compensates for a vertical step generated by the gate electrode. This solves various problems of semiconductor device production which are caused by the vertical step of the gate electrode. For example, the problem that the etching rate of the etching stop layer undesirably rises at the vertical step of the gate electrode during the etching process performed for forming a contact region by self-alignment contact is solved. Thus, the etching process is facilitated. In addition, the interlevel insulating layer on the gate electrode is more easily flattened.
Since the active region is not exposed after the source and drain regions are formed, the active region is not damaged by etching or ion implantation.
A semiconductor device according to the present invention includes a semiconductor substrate; a second conductivity type deep well region provided in the semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type shallow well region provided in the second conductivity type deep well regions; a gate insulating layer provided on the first conductivity type shallow well region; a gate electrode provided on the gate insulating layer; a gate electrode side wall insulating layer provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to portions of the gate electrode side wall insulating layer so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type shallow well region are electrically connected to each other, and the second conductivity type semiconductor layers are provided above the first conductivity type shallow well region and have a thickness which gradually increases from the device isolation region toward the gate electrode.
The structure according to the present invention can minimize the planar size of the junction of the source and drain regions and the well region of the dynamic threshold voltage transistor using a bulk substrate. Specifically, the distance from the gate electrode to the device isolation region in a gate length direction which is vertical to the longitudinal direction of the gate electrode can be reduced to about ⅔ L from the conventional value of 2.5 L to 3 L (L is the gate length and is usually a minimum processable size). The planar size of the junction is obtained by multiplying this value by a width W of the transistor. When the width W is the same, the planar size of the junction can be as small as about {fraction (4/15)} to {fraction (2/9)} of that of the conventional transistor. A planar component of the junction capacitance can also be as small as about {fraction (4/15)} to {fraction (2/9)} of that of the conventional transistor. Specifically, according to the present invention, as described above, the junction can be formed by implanting impurity ions to act as donors or acceptors for forming the source and drain regions only to the accumulated regions above the channel region and diffusing the impurity ions from the accumulated regions to the solid layer, i.e., the semiconductor substrate. Therefore, the junction can be formed at a shallow level. Consequently, a perimeter length component of the capacitance can be reduced. As described above, the present invention has advantages of reducing the parasitic resistance of the source and drain regions, effectively restricting the short channel effect, reducing the contact resistance with respect to the planar size of the source and drain regions, alleviating the undesirable thin line influence occurring at the time of siliciding reaction, and compensating for a vertical step generated by the gate electrodes.
In one embodiment, a surface of the source and drain regions is exposed to at least a portion of a contact hole for connecting the source and drain regions and the upper lines. The diameter of the contact hole can be larger than the width of the active region, i.e., the distance from an end of the gate electrode to the device isolation region in a cross-section taken along a direction vertical to the longitudinal direction of the gate electrode. Therefore, the diameter of the contact hole can be enlarged, which facilitates the formation of the contact hole. Conventionally, each of the contact holes needs to be entirely in the source or drain region. Accordingly, the contact hole needs to have a diameter which is smaller than the width of the source or drain region, and thus the processing for forming the contact hole is difficult.
In the structure of this embodiment also, the contact region can have a sufficient size when the length thereof in the longitudinal direction of the gate electrode is longer than the length thereof in the direction vertical to the longitudinal direction.
In one embodiment of the invention, the semiconductor device further includes contact holes for electrically connecting the source region and/or the drain region to upper lines. A width of each of the contact holes in a cross-section which is vertical to a longitudinal direction of the gate electrode is larger than a distance between the corresponding end of the gate electrode and the corresponding device isolation region. Therefore, the size of the contact hole can be increased without increasing the size of the source and drain regions. The ease of formation of the contact hole and the reduction in the junction capacitance (which depends on the planar size of the junction of the source and drain regions and the well region) can both be provided.
In one embodiment of the invention, a distance, in a direction which is vertical to a longitudinal direction of the gate electrode, between each end of the gate electrode and the corresponding device isolation region is smaller than a width of the gate electrode. Therefore, the planar size of the device is reduced, and also the parasitic capacitance at the junction of the source and drain regions and the well region is significantly reduced.
In one embodiment of the invention, the second conductivity type semiconductor layers acting as the source region and/or the drain region are formed of a material having an impurity diffusion coefficient which is larger than an impurity diffusion coefficient of the semiconductor substrate. Therefore, when the impurities are diffused and activated by heat treatment, the diffusion occurs very rapidly up to the interface between the accumulated layer and the semiconductor substrate but very slowly in the semiconductor substrate. In consequence, the depth of the level of the source and drain regions below the channel region is unlikely to be influenced by the dispersion in the height of the accumulated region, and thus the controllability on the impurity diffusion in the semiconductor substrate is improved. This allows the shallow junction to be formed with satisfactory controllability in the case of a bulk substrate, and allows the impurities to be diffused more easily in lateral directions in the channel region in the case of an SOI substrate.
The diffusion coefficient of the impurities in the second conductivity type semiconductor layers is preferably twice to 100 times as large as the diffusion coefficient of the impurities in the semiconductor substrate. In this case, the depth of the level of the source and drain regions below the channel region is unlikely to be influenced by the dispersion in the height of the accumulated region, and thus the controllability on the impurity diffusion in the semiconductor substrate is improved.
The second conductivity type semiconductor layers are preferably formed of polycrystalline silicon. Since polycrystalline silicon is often used in semiconductor device production, the need for introduction of new apparatuses or conditions is relatively small. Use of an enormous amount of hydrogen as required by a selective epitaxial growth apparatus is not necessary. The planar size of an apparatus for the device production is much smaller than a planar size of a selective epitaxial growth apparatus, which is very large partly due to the significant size of the hydrogen removal apparatus.
The polycrystalline silicon is preferably of column-like crystals. In this case, impurity diffusion in the polycrystalline silicon layer occurs very rapidly. The impurities doped into the polycrystalline silicon layer are diffused in the semiconductor substrate with satisfactory controllability. The depth of the level of the source and drain regions is unlikely to be influenced by the dispersion in the height of the polycrystalline silicon layer. Thus, the controllability on the impurity diffusion in the semiconductor substrate is improved.
When the grain size of the polycrystalline silicon is 50 nm or less, a diffusion coefficient larger than the diffusion coefficient in the semiconductor substrate can be realized. In addition, dispersion in the width of the side wall of the polycrystalline silicon layer which is caused by the grain of the polycrystalline silicon when etching back is performed can be suppressed.
In one embodiment of the invention, the gate electrode and the second conductivity type semiconductor layers each have a two-layer structure including a refractory metal silicide layer provided on a surface side of the semiconductor device and a polycrystalline silicon layer provided on a substrate side. Therefore, as described above, even the planar size of the contact region of the source and drain regions and the upper lines is small, the contact region can have a very low resistance. Since the suicide layer extends close to the channel region, the parasitic resistance can be restricted and thus the ability of the device for driving the current can be improved even when the planar size of the junction of the source and drain regions and the well region is small. The silicide layer can be used as an etching stop layer during the etching process for forming the contact hole.
A method for producing a semiconductor device according to the present invention includes the steps of forming device isolation regions, on a substrate including a first conductivity type semiconductor layer on a surface side, of a material which is resistant against silicon etching; sequentially forming a gate insulating layer, a gate electrode and a gate electrode side wall insulating layer on the first conductivity type semiconductor layer; forming a polycrystalline silicon layer having a thickness larger than a distance between the gate electrode and the device isolation regions over the entire surface of the resultant laminate; and performing anisotropic etching until a portion of the polycrystalline silicon layer which is on the gate electrode is eliminated.
A method for producing a semiconductor device according to the present invention includes the steps of forming device isolation regions, on a silicon substrate, of a material which is resistant against silicon etching forming a second conductivity type deep well region and forming a first conductivity type shallow well region in the second conductivity type deep well region; sequentially forming a gate insulating layer, a gate electrode, and a gate electrode side wall insulating layer on the first conductivity type well region; forming a polycrystalline silicon layer having a thickness larger than a distance between the gate electrode and the device isolation regions; and performing anisotropic etching until a portion of the polycrystalline silicon layer which is on the gate electrode is eliminated.
When the etching amount is set to such a value as to eliminate the polycrystalline silicon layer on the gate electrode for anisotropic etching back, the accumulated source and drain regions can easily be formed as in the present invention. Since the polycrystalline silicon layer has a thickness which is greater than the distance from the gate electrode to the device isolation region, the silicon substrate is not exposed. Thus, the silicon substrate is not damaged by anisotropic etching back. An end of the accumulated layer, on the side of the gate electrode, formed by anisotropic etching always extends onto the device isolation region formed of a material which is resistant to silicon etching. It should be noted that the accumulated layer formed of polycrystalline silicon layer on the side walls of the gate electrode needs to be divided into the source region and the drain region since the etching back process leaves the source region and the drain region shortcircuited.
When the source region of one semiconductor device and the drain region of an adjacent semiconductor substrate need to be connected to each other, such connection can be realized by setting the distance between adjacent gate electrodes of adjacent transistors connected in series to twice the thickness of the polycrystalline silicon layer to be accumulated or less.
A method for producing a semiconductor device according to the present invention includes the steps of forming device isolation regions, on a substrate including a first conductivity type semiconductor layer on a surface side, of a material which is resistant against silicon etching; sequentially forming a gate insulating layer, a gate electrode, and a gate electrode side wall insulating layer on the first conductivity type semiconductor layer; forming a polycrystalline silicon layer having a thickness larger than a distance between the gate electrode and the device isolation regions over the entire surface of the resultant laminate; performing anisotropic etching until a portion of the polycrystalline silicon layer which is on the gate electrode is eliminated; removing a portion of the polycrystalline silicon layer for electrically separating a source region and a drain region from each other; removing a portion of the gate electrode which corresponds to a contact region of the gate electrode and the first conductivity type semiconductor layer; removing a portion of the gate insulating layer which is exposed by removing the portion of the gate electrode, thereby exposing a surface of the first conductivity type semiconductor layer; and forming a refractory metal silicide layer on the source region, the drain region and the gate electrode, and concurrently forming a refractory metal silicide layer on the exposed surface of the first conductivity type semiconductor layer, thereby shortcircuiting the gate electrode and the first conductivity type semiconductor layer.
A method for producing a semiconductor device according to the present invention includes the steps of forming device isolation regions, on a silicon substrate, of a material which is resistant against silicon etching; forming a second conductivity type deep well region and forming a first conductivity type shallow well region in the second conductivity type deep well region; sequentially forming a gate insulating layer, a gate electrode, and a gate electrode side wall insulating layer on the first conductivity type well region; forming a polycrystalline silicon layer having a thickness larger than a distance between the gate electrode and the device isolation regions; performing anisotropic etching until a portion of the polycrystalline silicon layer which is on the gate electrode is eliminated; removing a portion of the polycrystalline silicon layer for electrically separating a source region and a drain region from each other; removing a portion of the gate electrode which corresponds to a contact region of the gate electrode and the first conductivity type well region; removing a portion of the gate insulating layer which is exposed by removing the portion of the gate electrode, thereby exposing a surface of the first conductivity type well region; and forming a refractory metal silicide layer on the source region, the drain region and the gate electrode, and concurrently forming a refractory metal silicide layer on the exposed surface of the first conductivity type semiconductor layer, thereby shortcircuiting the gate electrode and the first conductivity type semiconductor layer.
In this manner, the source and drain regions accumulated in contact with the side walls of the gate electrode can be formed in a self-aligned manner. By performing general saliciding process, the gate electrode and the body region or the shallow well region of the second conductivity type can be concurrently connected to each other without any additional step.
In one embodiment of the invention, the step of removing a portion of the polycrystalline silicon layer for electrically separating the source region and the drain region from each other, and the step of removing a portion of the gate electrode which corresponds to a contact region of the gate electrode and the first conductivity type well region are concurrently performed. Therefore, the process can be simplified.
In one embodiment of the invention, the method for producing a semiconductor device further includes the step of introducing an impurity acting as a donor or an acceptor into the source region, the drain region and the gate electrode, wherein the introduction is concurrently performed to the source region, the drain region and the gate electrode by ion implantation.
In this manner, a surface channel-type device can be formed with a smaller number of ion implantation steps. As described above, the diffusion coefficient of the impurities in the layer forming the source and drain regions accumulated on the semiconductor substrate is larger than the diffusion coefficient of the impurities in the semiconductor substrate. Therefore, even when doping of the gate electrode with impurities and doping of the source and drain regions with impurities are concurrently performed, the device can be formed with satisfactory controllability so that a depletion region is not formed in the gate electrode, the impurities are not diffused through the gate oxide layer, or an offset structure is not generated (i.e., the impurities are not diffused to form the source and drain regions sufficiently close to the channel region).
In one embodiment of the invention, the semiconductor device is a CMOS device. Concurrently with the introduction of the impurity acting as the donor to the source region, the drain region and the gate electrode of an n-channel semiconductor device, donor impurity implantation into the contact region is performed for shortcircuiting the gate electrode and an n conductivity type shallow well region or the semiconductor substrate of a p-channel semiconductor device. Concurrently with the introduction of the impurity acting as the acceptor to the source region, the drain region and the gate electrode of the p-channel semiconductor device, acceptor impurity implantation into the contact region is performed for shortcircuiting the gate electrode and a p conductivity type shallow well region or the semiconductor substrate of the n-channel semiconductor device.
Accordingly, ion implantation for connecting the gate electrode and the body region or the shallow well region can be performed using only a usual CMOS process without requiring any additional step. Specifically, the impurity concentration of a surface of the body region or the shallow well region, which usually determines the threshold voltage of the device, is set to be low (5xc3x971016 to 5xc3x971018/cm3). For forming a contact region in the body region or the shallow well region in order to, for example, connect a metal line or the silicide layer (as according to the present invention) to the above-mentioned low concentration region, the impurity concentration of the contact region needs to be high (1020/cm3 or more). This indispensably requires ion implantation into the contact region. If the low concentration contact region contacts a metal or metal silicide layer, a Schottky connection occurs but not an ohmic connection.